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high performance, 12-bit, 12-channel decimating, lcd decdriver ? AD8387 rev. 0 information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ? 2005 analog devices, inc. all rights reserved. features high accuracy, high-resolution voltage outputs 1 mv channel matching 12-bit input resolution laser-trimmed outputs fast settling, high voltage drive 35 ns settling time to 0.25% into 150 pf load slew rate 420 v/s outputs to within 1.3 v of supply rails high update rates fast, 110 mhz clock programmable video reference (brightness) and full-scale (contrast) output levels flexible logic inv bit reverses polarity of video signal r/l reverses loading order of data isw selects frame/row or column/dot inversion dsw selects single or dual data bus mode output short-circuit protection 3.3 v logic, 11 v to 18 v analog supplies available in 80-lead, 12 mm 12 mm, tqfp e-pad applications lcd microdisplay driver functional block diagram dba(0:11) vid0 vid1 vid10 vid11 dbb(0:11) byp tsw gsw dsw clk xfr r/l vrl vrh isw inv two-stage latch two-stage latch two-stage latch two-stage latch scaling control dac dac dac dac sequence control thermal switch bias g-mode switch 12 12 12 12 12 12 12 12 12 12 05653-001 AD8387 figure 1. general description the AD8387 decdriver provides dual, fast latched, 12-bit decimating input, which drives 12 high voltage outputs. twelve- bit input words are loaded into 12 separate high speed, bipolar dacs sequentially. flexible digital input format allows more than one AD8387 to be used in parallel for higher resolution displays. the output signal can be adjusted for dc reference, signal inversion, and contrast for maximum flexibility. the AD8387 is fabricated on adis fast bipolar, 26 v xfcb process, providing fast input logic, bipolar dacs with trimmed accuracy and fast settling, high voltage, precision drive amplifiers on the same chip. the AD8387 dissipates 1.34 w nominal static power. the AD8387 is offered in an 80-lead tqfp e-pad package and operates over the commercial temperature range of 0c to +85c. 5 0 0 05653-015 internal ambient temperature ( c) vde channel matching (mv) 4 3 2 1 10 20 30 40 50 60 70 80 normal projector operating temperature range code 4095 code 0 code 2048 figure 2. channel matching vs. temperature
AD8387 rev. 0 | page 2 of 16 table of contents features .............................................................................................. 1 applications ....................................................................................... 1 functional block diagram .............................................................. 1 general description ......................................................................... 1 revision history ............................................................................... 2 specifications ..................................................................................... 3 absolute maximum ratings ............................................................ 5 exposed paddle ............................................................................. 5 overload protection ..................................................................... 5 maximum power dissipation ..................................................... 5 operating temperature range ................................................... 5 esd caution .................................................................................. 5 pin configuration and function descriptions ............................. 6 typical performance characteristics ............................................. 8 timing diagrams .............................................................................. 9 single data bus configuration, dsw = low ......................... 9 dual data bus configuration, dsw = high ........................ 10 functional description .................................................................. 12 reference and control input description ............................... 12 theory of operation ...................................................................... 13 transfer function and analog output voltage ...................... 13 accuracy ...................................................................................... 13 applications ..................................................................................... 14 optimized reliability with the thermal switch .................... 14 initial power-up after assembly or repair ............................ 14 power-up during normal operation ..................................... 14 power supply sequencing ......................................................... 14 power-on sequence ................................................................... 14 power-off sequence ................................................................... 14 grounded output mode during power-off .......................... 14 pcb design for optimized thermal performance ............... 14 thermal pad design .................................................................. 15 thermal via structure design .................................................. 15 AD8387 pcb design recommendations ............................... 15 outline dimensions ....................................................................... 16 ordering guide .......................................................................... 16 revision history 10/05revision 0: initial version
AD8387 rev. 0 | page 3 of 16 specifications t a = 25c, avcc = 15.5 v, dvcc = 3.3 v, vrh = 9.5 v, vrl = 7 v, t a min = 0c, t a max = 75c still air, unless otherwise noted. table 1. parameter conditions min typ max unit video dc performance 1 t a min to t a max ,vfs = 5 v vdedifferential error voltage @ dac code 0 ?5.5 ?0.8 +5.0 mv @ dac code 1024 ?4.4 ?0.5 +3.6 mv @ dac code 2048 ?3.6 ?0.3 +3.3 mv @ dac code 3072 ?2.8 ?0.3 +2.8 mv @ dac code 4095 ?2.1 +0.2 +2.1 mv dac code range 0 to 4095 ?6.0 +6.0 mv vcmecommon-mode error voltage @ dac code 0 ?2.5 ?0.3 +2.5 mv @ dac code 1024 ?2.5 ?0.3 +2.5 mv @ dac code 2048 ?2.5 ?0.3 +2.5 mv @ dac code 3072 ?2.5 ?0.3 +2.5 mv @ dac code 4095 ?2.5 ?0.3 +2.5 mv dac code range 0 to 4095 ?3.5 +3.5 mv vdevde channel matching @ dac code 0 1.9 4.8 mv @ dac code 1024 1.8 4.3 mv @ dac code 2048 1.6 4.0 mv @ dac code 3072 1.4 3.8 mv @ dac code 4095 1.0 2.8 mv dac code range 0 to 4095 5.5 mv vchannel matching @ dac code 0 2.7 mv @ dac code 1024 2.7 mv @ dac code 2048 2.5 mv @ dac code 3072 2.5 mv @ dac code 4095 2.0 mv dac code range 0 to 4095 7.5 mv dnl 2 ?1 ?0.2 lsb video output dynamic performance t a min to t a max data switching settling time to 0.25% vidx = 5 v step, c l = 150 pf 35 50 ns data switching settling time to 1% 22 28 ns data switching slew rate 20% to 80% 420 v/s clk and data feedthrough 3 15 mv p-p all-hostile crosstalk 4 amplitude 69 mv p-p glitch duration 50 ns dac transition glitch energy dac code 2047 to 2048 0.4 nv-s invert switching settling time to 0.25% vidx = 10 v step, c l = 150 pf 70 150 ns invert switching settling time to 1% 34 40 ns invert switching slew rate 20% to 80% 700 v/s invert switching overshoot 25 mv
AD8387 rev. 0 | page 4 of 16 parameter conditions min typ max unit video output characteristics output voltage swing avcc ? voh, vol ? agnd 0.9 1.3 v output voltagegrounded mode 0.06 0.150 v data switching delay: t 7 5 vidx = 5 v step 15.7 ns data switching delay skew: t 7 5 4 ns inv switching delay: t 8 6 vidx = 10 v step 16.2 ns inv switching delay skew: t 8 6 4 ns output current 100 ma output resistance 28 reference inputs vrl range vrh vrl 5.25 avcc ? 4 v vrh range vrh vrl vrl vrl + 2.75 v vrh to vrl range 1 0 2.75 v vrh input resistance to vrl 22 k vrl input current ?44 a vrh input current 111 a resolution binary coding 12 bits digital input characteristics t a min to t a max clk input duty cycle 40% to 60% clk frequency dsw = high 110 mhz dsw = low 85 mhz data setup time: t 1 0 ns xfr setup time: t 3 0 ns data hold time: t 2 3.5 ns xfr hold time: t 4 3.5 ns clk high time: t 5 dsw = high 2.5 ns clk low time: t 6 dsw = high 3.0 ns clk high time: t 7 dsw = low 3.5 ns clk low time: t 8 dsw = low 4.0 ns c in 3 pf i ih 0.05 a i ih tsw 333 a i ih xfr 0.05 a i il ?0.6 a i il tsw ?1.3 a i il xfr ?1.2 a v ih 2 v v il 0.8 v v th 1.65 v power supplies dvcc, operating range 3 3.3 3.6 v dvcc, quiescent current 54 70 ma avcc, operating range 11 18 v avcc, quiescent current 75 100 ma operating temperature ambient temperature range, t a 7 still air, tsw = low 0 75 c ambient temperature range, t a 7 200 lfm airflow, tsw = low 0 85 c 1 vde = differential error voltage, vcme = common-mode error voltage, vde = vde matching between outputs, v = maximum deviation between outputs, and full-scale output voltage = vfs = 2 (vrh ? vrl). see the accuracy section. 2 guaranteed monotonic by characterization to four sigma limits. 3 measured on two outputs differentially as clk an d dbx(0:11) are driven and xfr is held low. 4 measured on two outputs differentially as the others are transitioning by 5 v. measured for both states of inv. 5 measured from 50% of rising clk edge to 50% of output change. measurement is made for both states of inv. 6 measured from 50% of inv transition to 50% of output change. 7 operation at elevated ambient temperature requires a thermally op timized pcb and additional thermal management, such as airflow across the surface of the AD8387.
AD8387 rev. 0 | page 5 of 16 absolute maximum ratings table 2. parameter rating supply voltages avccx ? agndx 18 v dvcc ? dgnd 4.5 v input voltages maximum digital input voltage dvcc + 0.5 v minimum digital input voltage dgnd ? 0.5 v maximum analog input voltage avcc + 0.5 v minimum analog input voltage agnd ? 0.5 v internal power dissipation 1 tqfp e-pad @ t a = 25c 4.38 w operating temperature range 0c to 85c storage temperature range ?65c to +125c lead temperature range (soldering 10 sec) 300c 1 80-lead tqfp e-pad: ja = 28.5c/w (still air) [jedec standard, 4-layer pcb in still air] jc = 12.2c/w jb = 14.6c/w jb = 12.0c/w jt = 0.3c/w. stresses above those listed under the absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to the absolute maximum ratings for extended periods may reduce device reliability. exposed paddle to ensure optimized thermal performance, the exposed paddle must be thermally connected to an external plane, such as avcc or gnd, as described in the applications section. overload protection the AD8387 overload protection circuit consists of an output current limiter and a thermal switch. when tsw is low, the thermal switch is disabled and the output current limiter is enabled. the maximum current at any one output is internally limited to 100 ma average. in the event of a momentary short-circuit between a video output and a power supply rail (vcc or agnd), the output current limit is sufficiently low to provide temporary protection. when tsw is high, the output current limiter, as well as the thermal switch, is enabled. the thermal switch debiases the output amplifier when the junction temperature reaches the internally set trip point. in the event of an extended short- circuit between a video output and a power supply rail, the output amplifier current continues to switch between 0 and 100 ma typical with a period determined by the thermal time constant and the hysteresis of the thermal trip point. the thermal switch, when enabled, provides long-term protection from accidental shorts during the assembly process by limiting the average junction temperature to a safe level. maximum power dissipation the maximum power that the AD8387 can safely dissipate is limited by its junction temperature. the maximum safe junction temperature for plastic encapsulated devices, as determined by the glass transition temperature of the plastic, is approximately 150c. exceeding this limit temporarily can cause a shift in the parametric performance due to a change in the stresses exerted on the die by the package. exceeding a junction temperature of 150c for an extended period can result in device failure. operating temperature range to ensure operation within the specified operating temperature range, it is necessary to limit the maximum power dissipation as follows. still air 200lfm 500lfm 1.0 maximum power dissipation (w) 3.0 50 55 60 65 70 75 80 85 90 10095 75 80 85 90 95 100 105 110 115 125120 ambient temperature ( c) thermal switch disabled enabled 05653-002 2.5 2.0 1.5 quiescent figure 3. maximum power dissipation vs. temperature, AD8387 on a 4-layer jedec pcb with thermally optimized landing pattern as described in the applications section esd caution esd (electrostatic discharge) sensitive device. electros tatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge wi thout detection. although this product features proprietary esd protection circuitry, permanent dama ge may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality.
AD8387 rev. 0 | page 6 of 16 pin configuration and fu nction descriptions 2 dba6 3 dba7 4 dba8 7 dba11 6 dba10 5 dba9 1 dba5 8 xfr 9 dvcc1 10 dgnd1 12 dsw 13 r/l 14 dbb11 15 dbb10 16 dbb9 17 dbb8 18 dbb7 19 dbb6 20 dbb5 11 clk 59 58 57 54 55 56 60 53 52 agnd1, 2 vid2 avcc2, 3 vid4 agnd3, 4 vid3 vid1 avcc4, 5 vid5 51 agnd5, 6 49 avcc6, 7 48 vid7 47 agnd7, 8 46 vid8 45 avcc8, 9 44 vid9 43 agnd9, 10 42 vid10 41 avcc10, 11 50 vid6 pin 1 nc = no connect 21 dbb4 22 dbb3 23 dbb2 24 dbb1 25 dbb0 26 dvcc3 27 dgnd3 28 isw 29 inv 30 gsw 31 tsw 32 agndb 33 agndb 34 avccb 35 avccb 36 byp 37 tsta 38 nc 39 agnd11 40 vid11 80 dba4 79 dba3 78 dba2 77 bba1 76 dba0 75 dvcc2 74 dgnd2 73 nc 72 nc 71 nc 70 agndd 69 agndd 68 avccd 67 avccd 66 vrh 65 vrh 64 vrl 63 agnd0 62 vid0 61 avcc0, 1 AD8387 top view (not to scale) 05653-004 figure 4. 80-lead tqfp e-pad pin configuration
AD8387 rev. 0 | page 7 of 16 table 3. 80-lead tqfp e-pad pin configurations pin no. mnemonic function description 1 to 7, 76 to 80; dba(0:11) data input 12-bit data input for even ch annels. vid(0, 2, 4, 6, 8, 10), msb = dba11. 14 to 25 dbb(0:11) data input 12-bit data input for od d channels. vid(1, 3, 5, 7, 9, 11), msb = dbb11. 8 xfr transfer/start sequence simultaneously initiates a new data loading sequence and transfers data loaded previously, to the outputs. 9, 26, 75 dvccx digital power supplies digital power supplies. 10, 27, 74 dgndx digital ground these pins are normally connected to the digital ground plane. 11 clk clock clock input. 12 dsw data mode switch selects single buss or dual buss operating modes. 13 r/l right/left select selects left direction or right direction operating mode. 28 isw invert mode switch enables and disables column inversion. 29 inv invert changes the polarity of the analog output signals. 30 gsw output mode switch enable s and disables grounded mode. 31 tsw thermal switch enables and disables long-term output protection. 32, 33, 39, 43, 47, 51, 55, 59, 63, 69, 70 agndx analog ground analog supply returns. 34, 35, 41, 45, 49, 53, 57, 61, 67, 68 avccx analog power supplies analog power supplies. 36 byp bypass a 0.1 f capacitor connected between byp and agnd ensures optimum settling time. 37 tsta test pin connect this pin to agnd. 38, 71 to 73 nc nc no connect. no internal connection. 40, 42, 44, 46, 48, 50, 52, 54, 56, 58, 60, 62 vid0 to vid11 analog outputs these pins are connected directly to the analog inputs of the lcd panel. 64 vrl video center reference this voltage sets the video center voltage. the video outputs are above this reference while inv = high and below this reference while inv = low. 65, 66 vrh full-scale reference twice the voltage applied between vrh and vrl sets the full-scale video output voltage.
AD8387 rev. 0 | page 8 of 16 typical performance characteristics 5.0 0 0 4096 05653-016 input code channel matching (mv) 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 512 1024 1536 2048 2560 3072 3584 vn vde vp figure 5. channel matching vs. code @ t a = 25c 5 ?5 0 4096 05653-018 input code vde (mv) 4 3 2 1 0 ?1 ?2 ?3 ?4 512 1024 1536 2048 2560 3072 3584 figure 6. vde vs. code 1.0 ?1.0 0 4096 05653-017 input code dnl (lsb) 0.8 0.6 0.4 0.2 0 ?0.2 ?0.4 ?0.6 ?0.8 512 1024 1536 2048 2560 3072 3584 figure 7. dnl vs. code @ t a = 25c, inv = h 5.0 0 0 05653-019 ambient temperature ( c) vde channel matching (mv) 4.0 3.0 2.0 1.0 0.5 4.5 3.5 2.5 1.5 10 20 30 40 50 60 70 80 code 4095 code 0 code 2048 figure 8. channel matching vs. t a @ codes 0, 2048, 4095 3.5 ?3.5 0 4096 05653-021 input code vcme (mv) 512 1024 1536 2048 2560 3072 3584 2.5 1.5 0.5 ?0.5 ?1.5 ?2.5 figure 9. vcme vs. code 1.0 ?1.0 0 4096 05653-020 input code dnl (lsb) 0.8 0.6 0.4 0.2 0 ?0.2 ?0.4 ?0.6 ?0.8 512 1024 1536 2048 2560 3072 3584 figure 10. dnl vs. code @ t a = 25c, inv = l
AD8387 rev. 0 | page 9 of 16 timing diagrams single data bus configuration, dsw = low vid0 vid1 vid2 vid3 vid4 vid5 vid6 vid7 vid8 vid9 vid10 vid11 channel 0 channel 1 channel 2 channel 3 channel 4 channel 5 channel 6 channel 7 channel 8 channel 9 channel 10 channel 11 dbb(0:11) dba(0:11) clk xfr r/l inv d(0:11) clk xfr r/l inv vrh isw vrl dsw 12-channel lcd references AD8387 image processor 2 pixel clk vrh vrl 12 05653-005 figure 11. AD8387 in single data bus system inputs inputs outputs outputs clk clk d(0:11) d(0:11) xfr xfr r/l r/l pixel clk pixel clk 12 0 ?12 vid0 13 1 ?11 vid1 14 2 ?10 vid2 15 3 ?9 vid3 16 4 ?8 vid4 17 5 ?7 vid5 18 6 ?6 vid6 19 7 ?5 vid7 20 8 ?4 vid8 21 9 ?3 vid9 22 10 ?2 vid10 23 11 ?1 vid11 23 11 ?1 vid0 22 10 ?2 vid1 21 9 ?3 vid2 20 8 ?4 vid3 19 7 ?5 vid4 18 6 ?6 vid5 17 5 ?7 vid6 16 4 ?8 vid7 15 3 ?9 vid8 14 2 ?10 vid9 13 1 ?11 vid10 12 0 ?12 vid11 left right ? 3 ? 3 0 0 1 1 2 2 3 3 4 4 5 5 6 6 7 7 8 8 9 9 10 10 11 11 13 13 14 14 15 15 16 16 17 17 18 18 19 19 20 20 21 21 22 22 23 23 24 24 12 ? 1 ? 2 ? 1 ? 2 05653-006 12 figure 12. AD8387 in single da ta bus configuration scanning left-to-right and right-to-left
AD8387 rev. 0 | page 10 of 16 dual data bus configuration, dsw = high vid0 vid1 vid2 vid3 vid4 vid5 vid6 vid7 vid8 vid9 vid10 vid11 channel 0 channel 1 channel 2 channel 3 channel 4 channel 5 channel 6 channel 7 channel 8 channel 9 channel 10 channel 11 dbb(0:11) dba(0:11) clk xfr r/l inv db(0:11) da(0:11) clk xfr r/l inv vrh isw vrl dsw 12-channel lcd AD8387 image processor 2 pixel clk 12 12 dvcc 05653-007 references vrh vrl figure 13. AD8387 in dual data bus system inputs outputs 2 3 64 75 108 119 14 15 1816 1917 22 23 24 25 20 21 dba(0:11) dbb(0:11) clk xfr r/l pixel clk 12 0 ?12 vid0 13 1 ?11 vid1 14 2 ?10 vid2 15 3 ?9 vid3 16 4 ?8 vid4 17 5 ?7 vid5 18 6 ?6 vid6 19 7 ?5 vid7 20 8 ?4 vid8 21 9 ?3 vid9 22 10 ?2 vid10 23 11 ?1 vid11 ?2 12 0 ?1 13 1 left inputs outputs 2 3 64 75 108 119 14 15 1816 1917 22 23 24 25 20 21 dba(0:11) dbb(0:11) clk xfr r/l pixel clk 23 11 ?1 vid0 22 10 ?2 vid1 21 9 ?3 vid2 20 8 ?4 vid3 19 7 ?5 vid4 18 6 ?6 vid5 17 5 ?7 vid6 16 4 ?8 vid7 15 3 ?9 vid8 14 2 ?10 vid9 13 1 ?11 vid10 12 0 ?12 vid11 ?1 13 1 right ?2 0 12 05653-008 figure 14. AD8387 in dual data bus configur ation scanning left-to-right and right-to-left
AD8387 rev. 0 | page 11 of 16 t 6 t 2 t 1 t 4 t 3 clk db(0:11) xfr v th v th v th t 1 t 2 t 5 05653-009 figure 15. input timing (dsw = low) db(0:11) xfr inv v id(0:11) t 8 vrl 50% vrl vrl + vfs vrl?vfs clk ?2 15 t 7 t 7 pixels ?12, ?11, ?10, ?9, ?8, ?7, ?6, ?5, ?4, ?3, ?2, ?1 pixels 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11 ?1 1 2 3 4 5 6 7 8 9 10 11 13 14 05653-010 12 0 figure 16. output timing (dsw = low) table 4. parameter conditions in t a nit data setup time: t 1 0 ns xfr setup time: t 3 0 ns data hold time: t 2 3.5 ns xfr hold time: t 4 3.5 ns clk high time: t 5 dsw = high 2.5 ns clk low time: t 6 dsw = high 3.0 ns clk high time: t 7 dsw = low 3.5 ns clk low time: t 8 dsw = low 4.0 ns data switching delay: t 7 15.7 ns data switching delay skew: t 7 vidx = 5 v step 4 ns invert switching delay: t 8 16.2 ns invert switching delay skew: t 8 4 ns
AD8387 rev. 0 | page 12 of 16 functional description the AD8387 is a system building block designed to directly drive the columns of lcd microdisplays of the type popularized for use in projection systems. it has 12 channels of precision, 12-bit dacs loaded from a dual, high speed, 12-bit wide input. precision current feedback amplifiers, providing well damped pulse response and fast voltage settling into large capacitive loads, buffer the 12 outputs. laser trimming at the wafer level ensures low absolute output errors and tight channel-to-channel matching. tight part-to-part matching in high resolution systems is guaranteed by the use of external voltage references. reference and control input description data transfer/start sequence controlinput data loading, data transfer a valid xfr is initiated when it is held high during a rising clk edge. data is transferred to the outputs and a new loading sequence is initiated on the next rising clk edge, immediately following a valid xfr. during a loading sequence, 12-bit words are loaded sequentially into 12 internal channels. when the AD8387 is configured for single data bus (dsw = low), data is loaded on both the rising and falling edges of clk. when configured for dual data bus (dsw = high), data is loaded on the rising edges of clk only. dsw controldata mode switch when this input is high, the AD8387 is in dual data bus mode. data is loaded from both dba(0:11) and dbb(0:11) on the rising clk edge simultaneously. r/l does not change the active clk edge in dual data bus mode. when low, the AD8387 is in single data bus mode. data is loaded on the rising clk edge from dba(0:11) and on the falling clk edge from dbb(0:11) when r/l is low. with r/l high, data is loaded on the falling clk edge from dba(0:11) and on the rising clk edge from dbb(0:11). right/left controlinput data loading to facilitate image mirroring, the direction of the loading sequence is set by the r/l control. a new loading sequence begins at channel 0 and proceeds to channel 11 when the r/l control is held low. it begins at channel 11 and proceeds to channel 0 when the r/l control is held high. tsw controlthermal switch control when this input is high, the thermal switch is enabled. when low or left unconnected, the thermal switch is disabled. an internal, 10 k pull-down resistor disables the thermal switch when this pin is left unconnected. gsw controloutput mode switch when this input is high, the video outputs operate normally. when low or left open, the video outputs are forced to agnd. this function operates when avcc power is off but requires dvcc power to be on. inv control and isw controlanalog output inversion when isw = low, the analog outputs transfer function is below vrl, while inv is held low, and is above vrl, while inv is held high. with isw = high, the analog outputs transfer function is above vrl for vid(0, 2, 4, 6, 8, 10) and is below vrl for vid(1, 3, 5, 7, 9, 11), while inv is held high. conversely, the analog outputs transfer function is below vrl for vid(0, 2, 4, 6, 8, 10) and is above vrl for vid(1, 3, 5, 7, 9, 11), while inv is held low. vrh, vrl inputsfull-scale video reference inputs two times the difference between vrh and vrl (analog input voltages) sets the full-scale output voltage. vfs = 2 ( vrh ? vrl )
AD8387 rev. 0 | page 13 of 16 theory of operation transfer function and analog output voltage the decdriver has two regions of operation where the video output voltages are either above or below the reference voltage vrl. the transfer function defines the video output voltage as the function of the digital input code as: voutn ( n) = vidx ( n) = vrl + vfs (1 ? n/4095), for inv = high voutp ( n) = vidx ( n) = vrl ? vfs (1 ? n/4095), for inv = low where n is the input code. vfs = 2 ( vrh ? vrl ) a number of internal limits define the usable range of the video output voltages, vidx, as shown in figure 17 . vidx ? volts avcc (vrl + vfs) vrl (vrl ? vfs) agnd 0 vidx vs. input code input code voutp voutn 4095 1.3v 0 vfs 5.25v 0 vfs 5.25v 1.3v 5.25v vrl (avcc ? 4) 11v avcc 18v internal limits and usable voltage ranges 05653-011 figure 17. AD8387 transfer function and usable voltage ranges accuracy to best correlate transfer function errors to image artifacts, the overall accuracy of the decdriver is defined by three parameters, vde , vcme, and vde. vde , the differential error voltage, measures the difference between the rms value of a channel and the ideal rms value of that channel. the defining expression is voutn(n) voutp(n) n vde(n) 1 vfs 24 0 9 ?? ? ?? ?? =? ? ?? ?? 5 vcme , the common-mode error voltage, measures ? the dc bias of a channel. the defining expression is ? ? ? ? ? ? ? + = vrl nvoutp nvoutn nvcme 2 )()( 2 1 ) ( vde measures the maximum vde mismatch between channels. the defining equation is vde = max { vde ( n ) ( 0 ? 11) } ? min {vde ( n ) ( 0 ? 11 ) } v measures the maximum mismatch between channels. the defining expression is v ( n ) = max { vn ( n ), vp ( n )} where: vn ( n ) = max { voutn ( n ) ( 0 ? 11) } ? min { voutn ( n ) ( 0 ? 11 ) } vp ( n ) = max { voutp ( n ) ( 0 ? 11 ) } ? min { voutp ( n ) ( 0 ? 11 ) }
AD8387 rev. 0 | page 14 of 16 applications optimized reliability with the thermal switch while internal current limiters provide short-term protection against temporary shorts at the outputs, the thermal switch provides protection against persistent shorts lasting for several seconds. to optimize reliability with the use of the thermal switch, the following sequence of operations is recommended. initial power-up after assembly or repair grounded output mode is disabled, and thermal switch is enabled. ensure that the gsw pin is high and that the tsw pin is high upon initial power-up and that they remain unchanged throughout this procedure. the initial power-up sequence follows: 1. execute the initial power-up. 2. identify any shorts at outputs. power down, repair shorts, and repeat the initial power-up sequence until proper system functionality is verified. 3. disable the thermal switch. power-up during normal operation grounded output mode is disabled, and thermal switch is disabled. if tsw = low and gsw = high, all outputs go into normal operating mode with the thermal switch disabled. power supply sequencing as indicated under the absolute maximum ratings , the voltage at any input pin cannot exceed its supply voltage by more than 0.5 v. power-on and power-off sequencing can be required to comply with the absolute maximum ratings. failure to comply with the absolute maximum ratings can result in functional failure or damage to the internal esd diodes. damaged esd diodes can cause temporary parametric failures, which can result in image artifacts. damaged esd diodes cannot provide full esd protection, reducing reliability. power-on sequence 1. turn on avcc 2. tur n on v rh 3. tur n on v rl 4. turn on dvcc 5. disable thermal switch: tsw = low 6. turn on input signals power-off sequence 1. tur n of f input s ig na ls 2. tur n of f vrl 3. tur n of f vrh 4. turn off avcc 5. tur n of f dvc c grounded output mode during power-off certain applications require that video outputs be held near agnd during power-down. the following power-off sequence ensures that the outputs are near ground during power-off and that the absolute maximum ratings are not violated. 1. enable grounded output mode: gsw = low 2. tur n of f input s ig na ls 3. tur n of f vrl 4. tur n of f vrh 5. turn off avcc 6. tur n of f dvc c pcb design for optimized thermal performance although the maximum safe operating junction temperature is higher, the AD8387 is 100% tested at a junction temperature of 125c. consequently, the maximum guaranteed operating junction temperature is 125c. to limit the maximum junction temperature at or below the guaranteed maximum, the package in conjunction with the pcb must effectively conduct heat away from the junction. the AD8387 package is designed to provide enhanced thermal characteristics through the exposed die paddle on the bottom surface of the package. to take full advantage of this feature, the exposed paddle must be in direct thermal contact with the pcb, which then serves as a heat sink. a thermally effective pcb must incorporate two thermal pads and a thermal via structure. the thermal pad on the top surface of the pcb provides a solderable contact surface on the top surface of the pcb. the thermal pad on the bottom pcb layer provides a surface in direct contact with the ambient. the thermal via structure provides a thermal path to the inner and bottom layers of the pcb to remove heat.
AD8387 rev. 0 | page 15 of 16 thermal pad design to minimize thermal performance degradation of production pcbs, the contact area between the thermal pad and the pcb should be maximized. therefore, the size of the thermal pad on the top pcb layer should match the exposed paddle. the second thermal pad of the same size should be placed on the bottom side of the pcb. at least one thermal pad should be in direct thermal contact with an external plane, such as avcc or gnd. thermal via structure design effective heat transfer from the top to the inner and bottom layers of the pcb requires thermal vias incorporated into the thermal pad design. thermal performance increases logarithmically with the number of vias. near optimum thermal performance of production pcbs is attained only when tightly spaced thermal vias are placed on the full extent of the thermal pad. thermal pad and ther mal via connections the thermal pad on the solder side is connected to a plane. the use of thermal spokes is not recommended when connecting the thermal pads or via structure to the plane. solder masking solder masking of the via holes on the top layer of the pcb plugs the via holes, inhibiting solder flow into the holes. to minimize the formation of solder voids due to solder flowing into the via holes (solder wicking), via diameter should be made small, and an optional solder mask can be used. to optimize the thermal pad coverage when using the solder mask, its diameter should be no more than 0.1 mm larger than the via hole diameter. pads are set by customers pcb design rules. thermal via holes circular mask, centered on the via holes. diameter of the mask should be 0.1 mm larger than the via hole diameter. solder maskbottom layer this is set by customers pcb design rules. 16mm 16mm 6.5mm 6.5mm 05653-012 figure 18. land pattern?top layer 6.5mm 6.5mm 05653-014 figure 19. land pattern?bottom layer 05653-013 figure 20. solder mask?top layer AD8387 pcb design recommendations table 5. land pattern dimensions pad size pad pitch thermal pad size thermal via structure 0.6 mm 0.25 mm 0.5 mm 6 mm 6 mm 0.25 mm ? 0.35 mm holes 0.5 mm ? 1.0 mm grid
AD8387 rev. 0 | page 16 of 16 outline dimensions compliant to jedec standards ms-026-add-hd 0.27 0.22 0.17 1 20 21 40 40 61 80 60 41 14.20 14.00 sq 13.80 12.20 12.00 sq 11.80 0.50 bsc lead pitch 0.75 0.60 0.45 1.20 max 1 20 21 61 80 60 41 1.05 1.00 0.95 0.20 0.09 0.08 max coplanarity view a rotated 90 ccw seating plane 0 min 7 3.5 0 0.15 0.05 view a pin 1 top view (pins down) 6.00 bsc sq bottom view (pins up) exposed pad figure 21. 80-lead thin quad flat package, exposed pad [tqfp_ep] (sv-80-1) dimensions shown in millimeters ordering guide model temperature range package description package option AD8387jsvz 1 0c to 85c 80-lead tqfp sv-80-1 AD8387-eb evaluation board 1 z = pb-free part. ? 2005 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d05653-0-10/05(0)

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